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Support #5747
closedcarrier 69, no ping
Start date:
01/06/2014
Due date:
% Done:
100%
Estimated time:
Description
The carrier master 69 is not able to be seen in the network (no ping).
After investigation, it seems that it is the FPGA principal that is not loaded (there is not LED 0)
I checked the tension, and tryed to modify them, but it did not change aanything.
Any idea?
-->ShowStatusADC
ShowStatusADC
POWER SUPPLY STATUS
IT | Desc | V Meas | V Targ | W | A | I | 0 | Vcc MGT | 1216 | 1200 | 336 | |||
1 | Vcc 3.3 In | 3344 | 3300 | 3712 | ||||||||||
2 | Vcc 1.8 Bf | 1823 | 1800 | 733 | ||||||||||
3 | Vcc core | 1263 | 1200 | * | 298 | |||||||||
4 | Vcc 5.0 In | 5168 | 5000 | * | 0 | |||||||||
5 | Vcc 2.5 IO | 2512 | 2500 | 4394 | ||||||||||
6 | Vcc 3.3 IO | 3343 | 3300 | 3730 | ||||||||||
7 | Vcc CMC #4 | 3472 | 3400 | 1385 | ||||||||||
8 | Vcc CMC #3 | 3439 | 3400 | 1780 | ||||||||||
9 | Vcc CMC #2 | 3455 | 3400 | 1694 | ||||||||||
10 | Vcc CMC #1 | 3455 | 3400 | 8304 |
Updated by Ralet Damian almost 11 years ago
- Priority changed from Urgent to High
After remooving the mezzanine, and changing the place of them, it worked, we can load the FPGA0.
Mezzanine 142 was inverted with 190.
Is it needed to flash/rewrite the EPROMs via the LINCOs?
Updated by Lafay Xavier almost 11 years ago
- Status changed from New to Resolved
- % Done changed from 0 to 100
Don't need to program FPGA's EPROM.
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